Powering Your FPGA/SoC the Easy Way with the New AmPX8EB1

There are about a million types of SoCs in the market! Okay maybe that’s a hyperbole, but how about at least 1000? And, likely, not one matches your needs perfectly. And that’s by design and by the virtue of FPGAs. However, powering an FPGA does not have to follow the same blueprint. You’re probably rolling your eyes and considering that yes, PMICs and discretes have existed forever addressing this problem, but what if I told you that programmable PMICs are a unique breed of products poised to solve this silly power problem and make it a thing of the past. Did you bite yet?

No?

Okay, give me 60 seconds and we’ll show you how.

Programmable PMICs from AnDAPT combine the best of the worlds of discretes, PMICs, and mixed-signal logic. They integrate analog, digital, and power, and then integrate some more and let you program and modify in case you can’t find a perfect solution in our existing portfolio of products covering the most popular FPGAs on the planet.

I know what you’re thinking now… Tell me more… isn’t it?

The recently released evaluation board AmPX8EB1’s whole purpose is to demonstrate the ready-to-use functionalities of powering the popular Xilinx Zynq UltraScale+ (ZU+) MPSoC family FPGA devices covering SKUs from the most basic ZU2CG devices to ZU5EV devices with video processing capabilities, serving up to 26 power supply rails using 2 PMICs!

The board showcases the architectural flexibility, high efficiency, and cost-effectiveness of the AmP8DB6QF65 PMIC configured in a performance-optimized use case.

Figure 1: Evaluation board & packaging for Xilinx Zynq UltraScale+ (ZU+) MPSoC family FPGA devices.

The design covers all required 26 power rails using two AmP8D6Q65 PMICs replacing over 15 discrete ICs (Figure 2, 3). Fewer ICs afford increased reliability by having fewer failure points, increased integration, and result in PCB space-savings. Each PMIC incorporates a single or two-phase DrMOS controller (up to 70 A), multiple buck converters (10 A/6 A), high current LDOs (up to 2 A) or load switches (LDSW), 4 general purpose LDOs (200 mA) and power management features including fault protection and sequencing.

Figure 2: Zynq UltraScale+ MPSoC Block Diagram.

Figure 3: AnDAPT Solution — Performance Optimized.

Figure 4: Evaluation board for Xilinx Zynq UltraScale+ (ZU+) MPSoC family FPGA devices.

The board is ready-to-use and comes pre-programmed with “performance-optimized” power tree mapping. The power map for the use case is accessible here.

More resources

• Quick start guide available here with instructions for programming, bring-up, debugging, schematics, layout, etc…
• A bring-up video to familiarize the user with the basics of the board, the setup, how to program it, and test various rails in the lab.
• With the board, users get access to the license-free configuration software, WebAmP R.D. which allows configuration and modification of design including changing turn-on/off sequencing, and enabling/disabling rails. Additional features include programmability, auto-BoM creation, and PCB area estimation. Learn how to modify the design here in the quick-start guide.

Figure 5: WebAmP R.D. excerpt showing a test report for Xilinx Zynq MPSoC XCZU5.

• The test report includes no load/full load ripple, transient, and efficiency data that has been verified and recommended by AMD Xilinx for meeting or exceeding Xilinx power specifications. AnDAPT is an official power partner with Xilinx with several AnDAPT power designs recommended by Xilinx. Check more designs out here.

For more information, visit us at www.andapt.com

Please contact us for any questions, comments, or feedback.

Authors:

• Ajit Narwal
• Giovanni Garcea

Further Reading:

• Powering SoCs and FPGAs with AnDAPT WebAmP R.D.
• AnDAPT News